> This is THE most important register in the microprocessor. Various machine language instructions allow you to copy the contents of a memory location into the accumulator, copy the contents of the accumulator into a memory location, modify the contents of the accumulator or some other register directly, without affecting any memory. And the accumulator is the only register that has instructions for performing math.
It has some other registers (X, Y, Status, Program Counter and Stack Pointer). Looking at the instruction set ( http://www.e-tradition.net/bytes/6502/6502_instruction_set.h... ) , you'll see that all of the math operands work off of the accumulator. X and Y are primarily for the offset for a memory location.
Thanks, architectures where the accumulator is always used implicitly then?
I have often heard "register based architecture" used to describe MIPS/load store type architectures. It seems that the author here is implying that the x86 is "register based" since they''re stating its not actually an "accumulator machine" does have an accumulator like register?
The definitions are not strict, and there is often significant overlap between the categorization types (esp. as follow-on additions are added to the initial designs).
But generally, things fall out this way:
1) register based
Has a pool of registers, and the registers are general purpose (meaning they can be used as source or destination for most any computation operation the CPU can perform).
2) accumulator based
Has a "dignified" register (the accumulator) and most computations only happen in/out of the accumulator. Other registers exist for more specialized purposes to facilitate feeding data into and out of the accumulator. Many DSP architectures are very highly "accumulator based". General purpose CPU's, less so unless you go back in time to late 70's or early 80's architectures.
3) stack based
Has no registers (or very few) other than a stack pointer. All temporary data is stored on the stack, and all computation instructions involve computing with data items at the top of the stack and returning the result to the top of the stack. An example of such an architecture was the HP3000 system from the 70's (https://en.wikipedia.org/wiki/HP_3000#Use_of_stack_instead_o...).
Thanks for the detailed explanations. I had a few questions about what you wrote:
>"Has a "dignified" register (the accumulator) and most computations only happen in/out of the accumulator."
I was curious about your use of the word dignified in quotes. Are you just conveying its importance or with this or something else?
>"Many DSP architectures are very highly "accumulator based". "
Is there something about DSP and their workloads that make accumulator based architectures a good fit?
>"All temporary data is stored on the stack, and all computation instructions involve computing with data items at the top of the stack "
So are computation limited to the top two positions of the stack then? As in the operands can be obtain by two pop operations and not arbitrary positions in the stack?
> I was curious about your use of the word dignified in quotes. Are you just conveying its importance or with this or something else?
Just conveying its importance. Since in a pure accumulator based architecture the accumulator is the only register into which computations can be performed, it often is quite important.
> Is there something about DSP and their workloads that make accumulator based architectures a good fit?
They often do a lot of operations that involve accumulating running totals of long strings of numbers, so the math operations they typically process lend themselves to a predisposition to being designed in this fashion. Beyond that I am unsure of any other reasons beyond guessing at possibilities.
> So are computation limited to the top two positions of the stack then?
Typically the number of stack top elements that are retrieved depend on the instruction being executed. So an add that consumes two inputs would take in the top two stack elements, and return a single sum. But an 'increment' (really just an add where one input is a constant) would only consume one stack element. There is no reason (other than the additional design complexity) that a three or four or five operand input instruction could not be designed, and it would consume its designed number of stack top positions.
> and not arbitrary positions in the stack?
Generally, no, in stack based systems one usually can not address arbitrary positions in the stack. However, there are always exceptions, and many systems have a "roll" operation that rotates the top X stack positions one place (a few provide a way to roll X stack top positions by Y steps), which provides a way to get at data below the top of the stack without loosing the current data that is at the top. With that said, there is probably at least one architecture that allows for specifically addressing particular stack positions without popping/rolling.
The PIC16 is probably the closest - all arithmetic has to go through the W register. Confusingly PIC calls all internal memory "registers", but really it's more like a one-register machine.
The Z80 routes most arithmetic through its A (accumulator) register.
The inheritor of this is the X86, where there are much fewer register limitations but tradition and the lettering remain; (E)AX is the calling convention's first argument and return parameter. And the article itself details that you can get shorter opcodes by preferring to do arithmetic through EAX.
In 6502, there is LDA, LDX, LDY for various loads. However, ADC (add with carry) only works on the accumulator.
Another important aspect of (at least the 6502) is a very limited instruction set. With addressing modes and op codes there are at most 256 of them (one byte). ADC with addressing modes is 8 of the 256 instructions. AND (bitwise and memory location with accumulator) is another 8. And so on. To add the corresponding op codes for the X and Y registers - beyond adding more transistors - adds more op codes which were also at a premium. Granted, there are 105 of the 256 that weren’t used, but to make the 6502 into a design that would more closely match a three register architecture rather than an accumulator architecture would significantly eat into the unused op codes. Hypothetical ADCX and ADCY would be 12 or 16 more op codes. Eight more opcodes with that fully support the X and Y registers would consume all of those potential instructions (only six more opcodes if the accumulator is allowable as an offset).
The terms aren't super-formally defined but "register based" usually suggests "has a bunch of general purpose registers", load store doesn't have to be a part of it. A 68k has a bunch of general purpose(ish) registers.
> THE ACCUMULATOR
> This is THE most important register in the microprocessor. Various machine language instructions allow you to copy the contents of a memory location into the accumulator, copy the contents of the accumulator into a memory location, modify the contents of the accumulator or some other register directly, without affecting any memory. And the accumulator is the only register that has instructions for performing math.
It has some other registers (X, Y, Status, Program Counter and Stack Pointer). Looking at the instruction set ( http://www.e-tradition.net/bytes/6502/6502_instruction_set.h... ) , you'll see that all of the math operands work off of the accumulator. X and Y are primarily for the offset for a memory location.